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LTC1923 Datasheet(PDF) 8 Page - Linear Technology |
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LTC1923 Datasheet(HTML) 8 Page - Linear Technology |
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8 / 28 page  8 LTC1923 1923f PI FU CTIO S PLLLPF (Pin 1/Pin 30): This pin serves as the lowpass filter for the phase-locked loop when the part is being synchronized. The average voltage on this pin equally alters both the oscillator charge and discharge currents, thereby changing the frequency of operation. Bringing the voltage on this pin above VDD – 0.4V signifies that the part will be used as the synchronization master. This allows multiple devices on the same board to be operated at the same frequency. The SDSYNC pin will be pulled low during each CT charging cycle to facilitate synchronization. RSLEW (Pin 2/Pin 31): Placing a resistor from this pin to AGND sets the voltage slew rate of the output driver pins. The minimum resistor value is 10k and the maximum value is 300k. Slew rate limiting can be disabled by tying this pin to VDD, allowing the outputs to transition at their maximum rate. SDSYNC (Pin 3/Pin 32): This pin can be used to disable the IC, synchronize the internal oscillator or be the master to synchronize other devices. Grounding this pin will disable all internal circuitry and cause NDRVA and NDRVB to be forced low and PDRVA and PDRVB to be forced to VDD. EAOUT will be forced low. FAULT will also be asserted low indicating a fault condition. The pin can be pulled low for up to 20 µs without triggering the shutdown circuitry. The part can either be slaved to an external clock or can be used as the master (see Applications Information for a more detailed explanantion). CNTRL (Pin 4/Pin 1): Noninverting Input to the Error Amplifier. EAOUT (Pin 5/Pin 2): Output of the Error Amplifier. The loop compensation network is connected between this pin and FB. The voltage on this pin is the input to the PWM comparator and commands anywhere between 0% and 100% duty cycle to control the temperature of the tem- perature sense element. FB (Pin 6/Pin 3): The Inverting Input to the Error Amplifier. This input is connected to EAOUT through a compensating feedback network. AGND (Pin 7/Pin 4): Signal Ground. All voltages are measured with respect to AGND. Bypass VDD and VREF with low ESR capacitors to the ground plane near this pin. SS (Pin 8/Pin 6): The TEC current can be soft-started by adding a capacitor from this pin to ground. This capacitor will be charged by a 1.5 µAcurrentsource.Thispinconnects to one of the inverting inputs of the current limit compara- tor and allows the TEC current to be linearly ramped up from zero. The voltage on this pin must be greater than 1.5V to allow the open/shorted thermistor window comparitor to signal a fault. ILIM (Pin 9/Pin 7): A voltage divider from VREF to this pin sets the current limit threshold for the TEC. If the voltage on this pin is set higher than 1V, then ILIMIT = 150mV/RS as that is the internal current limit comparator level. If the voltage on this pin is set less than 1V, the current limit value where the comparator trips is: ILIMIT = [0.15 • RILIM1 • VREF]/[(RILIM1 + RILIM2) • RS] VSET (Pin 10/Pin 8): This is the input for the setpoint reference of the temperature sense element divider net- work or bridge. This pin must be connected to the bias source for the thermistor divider network. FAULT (Pin 11/Pin 9): Open-drain output that indicates by pulling low when the voltage on VTHRM is outside the specified window, the part is in shutdown, undervoltage lockout (UVLO), or the reference is not good. When the voltage on VTHRM is outside the specified window, it signifies that the thermistor impedance is out of its accept- able range. This signal can be used to flag a microcontroller to shut the system down or used to disconnect power from the bridge. See Applications Information for using this signal for redundant protection. VTHRM (Pin 12/Pin 10): Voltage Across the Thermistor. If the voltage on this pin is outside the range between 410mV below VSET and 0.2 • VSET, the FAULT pin will be asserted (and latched) low indicating that the thermistor tempera- ture has moved outside the acceptable range. H/C (Pin 13/Pin 11): This open-drain output provides the direction information of the TEC current flow. If TEC+ is greater than TEC –, which typically corresponds to the system cooling, this output will be a logic low. If the opposite is the case, this pin will pull to a logic high. (GN Package/UH Package) |
Similar Part No. - LTC1923 |
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Similar Description - LTC1923 |
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