1

2001

Integrated Device Technology, Inc.

DSC-4512/1



APRIL 2001

3.3 VOLT CMOS SuperSync FIFO™

32,768 X 18

65,536 X 18

IDT72V275

IDT72V285

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

.EATURES:

IDT72V275

32,768 x 18

IDT72V285

65,536 x 18

settings

latency time

default to one of two preselected offsets

EF

EF

EF

EF and FF

FF

FF

FF

FF flags) or First Word

Fall Through timing (using

OR

OR

OR

OR

OR and IR

IR

IR

IR

IR flags)

simultaneously)

Slim Thin Quad Flat Pack (STQFP)

DESCRIPTION:

The IDT72V275/72V285 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs, including the following:

has been removed. The Frequency Select pin (FS) has been removed,

thus it is no longer necessary to select which of the two clock inputs, RCLK

or WCLK, is running at the higher frequency.

an empty FIFO to the time it can be read, is now fixed and short. (The

variable clock cycle counting delay associated with the latency period

found on previous SuperSync devices has been eliminated on this

SuperSync family.)

SuperSync FIFOs are particularly appropriate for network, video, telecom-

munications,datacommunicationsandotherapplicationsthatneedtobuffer

large amounts of data.

.UNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

32,768 x 18

65,536 x 18

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

HF

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

LD

MRS

REN

RCLK

OE

OFFSET REGISTER

PRS

FWFT/SI

SEN

RT

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