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ISL6744 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6744 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 18 page 7 FN9147.8 September 22, 2005 Pin Descriptions VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. The total supply current, IDD, will be dependent on the load applied to outputs OUTA and OUTB. Total IDD current is the sum of the quiescent current and the average output current. Knowing the operating frequency, Fsw, and the output loading capacitance charge, Q, per output, the average output current can be calculated from: RTD - This is the oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 55x this current. The PWM deadtime is determined by the timing capacitor discharge duration. CT - The oscillator timing capacitor is connected between this pin and GND. CS - This is the input to the overcurrent protection comparator. The overcurrent comparator threshold is set at 0.600V nominal. The CS pin is shorted to GND at the end of each switching cycle. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. Exceeding the overcurrent threshold will start a delayed shutdown sequence. Once an overcurrent condition is detected, the soft-start charge current source is disabled. The soft-start capacitor begins discharging through a 15µA current source, and if it discharges to less than 3.9V (Sustained Overcurrent Threshold), a shutdown condition occurs and the OUTA and OUTB outputs are forced low. When the soft-start voltage reaches 0.27V (Reset Threshold) a soft-start cycle begins. If the overcurrent condition ceases, and then an additional 50µs period elapses before the shutdown threshold is reached, no shutdown occurs. The SS charging current is re-enabled and the soft-start voltage is allowed to recover. GND - Reference and power ground for all functions on this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. OUTA and OUTB - Alternate half cycle output stages. Each output is capable of 1A peak currents for driving power MOSFETs or MOSFET drivers. Each output provides very low impedance to overshoot and undershoot. SS - Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor determines the rate of increase of the duty cycle during start-up, controls the overcurrent shutdown delay, and the overcurrent and short circuit hiccup restart period. Functional Description Features The ISL6744 PWM is an excellent choice for low cost bridge topologies for applications requiring accurate frequency and deadtime control. Among its many features are 1A FET drivers, adjustable soft-start, overcurrent protection and internal thermal protection, allowing a highly flexible design with minimal external components. Oscillator The ISL6744 has an oscillator with a frequency range to 2MHz, programmable using a resistor RTD and capacitor CT. The switching period may be considered to be the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and the internal current source (assumed to be 160µA in the formula). The discharge duration is determined by RTD and CT. where TC and TD are the approximate charge and discharge times, respectively, TOSC is the oscillator free running period, and FOSC is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times will be slightly longer than calculated due to internal propagation delays of approximately 5ns/transition. This delay adds directly to the switching duration, and also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low charge and discharge currents are used, there will be an increased error due to the input impedance at the CT pin. The above formulae help with the estimation of the frequency. Practically, effects like stray capacitances that affect the overall CT capacitance, variation in RTD voltage and charge current over temperature, etc. exist, and are best evaluated in-circuit. Equation 2 follows from the basic capacitor current equation, . In this case, with variation in dV with RTD (Figure 5), and in charge current (Figure 4), results from Equation 2 would differ from the calculated frequency. The typical performance curves may be used as a tool along with the above equations as a more accurate tool to estimate the operating frequency more accurately. The maximum duty cycle, D, and deadtime, DT, can be calculated from: IOUT 2QFsw • • = (EQ. 1) TC 1.25 4 ×10 CT • ≈ s (EQ. 2) TD 1 CTDisch eCurrentGain arg ----------------------------------------------------------------------------- RTD • CT • ≈ s (EQ. 3) TOSC TC TD + 1 FOSC ---------------- == s(EQ. 4) iC t d dV × = DTC TOSC ⁄ = (EQ. 5) DT 1 D – () T OSC ⋅ = s(EQ. 6) ISL6744 |
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