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AD9876BST Datasheet(PDF) 7 Page - Analog Devices |
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AD9876BST Datasheet(HTML) 7 Page - Analog Devices |
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7 / 24 page  REV. A AD9876 –7– DEFINITIONS OF SPECIFICATIONS CLOCK JITTER The clock jitter is a measure of the intrinsic jitter of the PLL generated clocks. It is a measure of the jitter from one rising and of the clock with respect to another edge of the clock nine cycles later. DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating ranges. INTEGRAL NONLINEARITY ERROR (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. PHASE NOISE Single-sideband phase noise power density is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly on a generated single tone with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. OUTPUT COMPLIANCE RANGE The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation, resulting in nonlinear per- formance or breakdown. SPURIOUS–FREE DYNAMIC RANGE (SFDR) The difference, in dB, between the rms amplitude of the DACs output signal (or ADCs input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth, unless otherwise noted). PIPELINE DELAY (LATENCY) The number of clock cycles between conversion initiation and the associated output data being made available. OFFSET ERROR First transition should occur for an analog value 1/2 LSB above negative full scale. Offset error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. INPUT REFERRED NOISE The rms output noise is measured using histogram techniques. The ADC output codes’ standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the Rx input of the AD9876. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the num- ber of bits. Using the following formula: N SINAD dB = () –. . 176 6 02 it is possible to get a measure of performance expressed as N, the effective number of bits. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. POWER SUPPLY REJECTION Power supply rejection specifies the converters maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages. |
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