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W27L01T-70 Datasheet(PDF) 3 Page - Winbond |
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W27L01T-70 Datasheet(HTML) 3 Page - Winbond |
3 / 15 page W27L01 Publication Release Date: February 20, 2003 - 3 - Revision A3 Two-line Output Control Since EPROMs are often used in large memory arrays, the W27L01 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VDD and Vss. This high frequency, low inherent-inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VDD and Vss. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. Table of Operating Modes VDD = 3.3V ±10%, Vpp = VpE = VHH = 12V, VCP = VPE = 5V, X = VIH or VIL PINS MODE #CE #OE #PGM A0 A9 VDD VPP OUTPUTS Read VIL VIL X X X VDD VDD DOUT Output Disable VIL VIH X X X VDD VDD High Z Standby (TTL) VIH X X X X VDD VDD High Z Standby (CMOS) VDD ±0.3V X X X X VDD VDD High Z Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCP VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VPE VCP VPE FF (Hex) Erase Verify VIL VIL VIH X X VPE VPP DOUT Erase Inhibit VIH X X X X VCP VPE High Z Product Identifier-Manufacturer VIL VIL X VIL VHH VDD VDD DA (Hex) Product Identifier-Device VIL VIL X VIH VHH VDD VDD 01 (Hex) |
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