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TK68HC24PRU Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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8 / 21 page Tekmos TK68HC24 PRU 8 www.Tekmos.com 8/21/99 mode may not be re-entered by writing the bit back to one. This SMOD bit becomes write-protected once written to zero. This implies that the normal operating mode can be entered either through a hardware reset or through software while the special test mode may only be entered through hardware reset. IRV – Bit 4, Read, write once The IRV (Internal Read Visibility) control bit eliminates potential bus conflict problems when this device is used in conjunction with the 68HC11. To allow a logic analyzer to monitor the internal bus activity of the 68HC11, provisions have been made for the MPU to selectively drive the external data bus during internal reads as well as writes. The selection of this feature is controlled by the IRV bit. The state following reset and the programming characteristics of the TK68HC24 IRV bit are the same as the 68HC11 IRV bit. However, the functional characteristics are the opposite. The TK68HC24 IRV functions as follows: Logic 0 – Reads of the INIT and HPRIO registers will enable the multiplexed address/data buffers, placing the contents of the selected register on the bus. Logic 1 – Reads of the INIT and HPRIO registers do not enable the multiplexed address/data bus drivers. This bit may be read at any time, although the multiplexed address/data bus will remain high-impedance during reads when IRV equals one. Only one write will be acknowledged and then only if SMOD equals one. The IRV bit is forced to zero (reads of HPRIO and INIT enabled) when SMOD is written from a one to a zero (entering normal mode). Resets clears this bit in the normal mode and sets this bit in the special test mode. b7, b5, b3, b2, b1, b0 – Not Implemented These bits are not implemented. Writes have no meaning or effect on them. Reads of these bits will always return a logic zero value. INIT (I/O MAPPING REGISTER) Reset value = 00000001 The INIT (I/O Mapping) register is a special purpose 8-bit register that is used (optionally) during initialization to change the default locations of the TK68HC24 internal registers in the MPU/MCU memory map. The lower four bits of the TK68HC24 INIT register are duplicates of the 68HC11 INIT register. These four bits are used to specify the active state of the four high order address bits to the register address decoding logic. This register functions identically to the 68HC11 INIT register with the following exceptions: 1) only the lower four bits are implemented, and 2) the protection mechanism is not time dependent. The default starting address of the 64-byte internal register space is $1x00 (i.e. INIT is initialized to $01). Initialization software can move registers to any 4K boundary within the memory map. External decoding of A8 through A11 specifies where in the 4K block (on 256-byte boundaries) the 64-byte register space is located. As an example, assume that the initialization software wrote the value $09 to the INIT register and that CS was true when A8 through A11 were low. This would place the registers from $9000 through $903F in the memory map. Decoding A8 through A11 so that the chip is selected when all four address lines are low maps the TK68HC24 registers to the same address as the 68HC11 registers. The INIT register is special in that there is a write- protect mechanism associated with it. In the normal mode, the register may be written once at any time after reset. This differs from the operation of the 68HC11 INIT register which becomes write protected after the first 64 E-clock cycles, whether or not a write to the register has occurred. After the first write, the INIT register becomes write-protected and thereafter is a read-only register. While in the special test mode (SMOD equals one), the protection mechanism is overridden and the INIT register may be written repeatedly as long as SMOD remains a one. When SMOD is written to a zero (to enter the normal operating mode), the write-protect mechanism is enabled. One additional write, regardless of the number of writes performed while in the special test mode, is allowed after entering normal operating mode. The upper four bits of the INIT register are unused, and will always read as zeros. |
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