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TK68HC24 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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TK68HC24 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 21 page Tekmos TK68HC24 PRU 10 www.Tekmos.com 8/21/99 interrupt), and deassert the READY line (STRB). Deassertion of the READY line would automatically inhibit the external device from strobing new data into Port C. Reading the PORTCL latch register, after reading PIOC with STAF set, clears the STAF flag. Whenever PORTCL is read, the READY (STRB) line is asserted indicating that new data may now be strobed in to Port C. The STRB line can be configured (with the PLS control bit) to be a pulse output (pulse mode) or a static output (interlocked mode). The only difference between the pulse and interlock modes is that in pulse mode, the READY line pulses (asserts) for only two E-clock periods after the latched data becomes available. While in interlock mode, the asserted state of the READY line lasts until new data is strobed into Port C via the STRA input line. The Port C DDR bits should be cleared (input) for each bit that is to be used as a latched input bit. It is, however, possible to use some Port C bits as latched inputs with the input handshake protocol and at the same time use other Port C bits as static inputs and still other Port C bits as static output bits. The input handshake protocol has no effect on the use of Port C bits as static inputs or static outputs. Reads of the PORTC register always return the static logic level at the Port C pins (for lines configured as input) or at the inputs to the pin drivers (for lines configured as outputs). Data latched into PORTCL always reflects the level at the Port C pins. Writes to either the PORTC address or the PORTCL address will write information to the Port C output register without affecting the input handshake strobes. NOTE: After programming PIOC to enter the input handshake mode, STRB will remain in the inactive state. The precaution has been taken to ensure that the external system will not strobe data into PORTCL before all initialization is complete. When ready to accept data, the MPU/MCU should perform a dummy read of the PORTCL address. This operation will assert STRB initiating the input handshake protocol. Output Handshake Protocol In the output handshake scheme, Port C is an output port, STRB is a READY output, and STRA is an edge-sensitive acknowledge input signal indicating that Port C output data has been accepted by the external device. In a variation of this output handshake operation, STRA is used as an output enable input as well as an edge-sensitive acknowledge input. In a typical system, the controlling processor writes to the TK68HC24, placing data in the Port C output latch. Stable data on the Port C pins is indicated by the automatic assertion of the TK68HC24 READY (STRB) line. The external device then processes the available data and pulses the STRA input to indicate the new data may be placed on the Port C output lines. The active edge on STRA causes the READY (STRB) line to be automatically deasserted and the STAF status flag to be set (optionally causing an interrupt). In response to STAF being set, the program puts out new data on Port C as required. There are two addresses associated with the Port C data register, the normal PORTC data address and a second address (PORTCL) that accesses the input latch on reads and the normal port on writes. On writes to the second address (PORTCL), the data goes to the same port output register as it would on a write to the PORTC address but the STAF flag bit is cleared (provided PIOC was first read with the STAF bit set). This allows an automatic clearing mechanism in output handshake modes to co-exist with normal Port C outputs. All eight bits in Port C must be used as outputs while the output handshake protocol is selected. That is, part of Port C may not be used for static or latched inputs while the remaining bits are being used for output handshake. The following paragraphs cover this limitation in more detail. Output Handshake Protocol, Three-State Variation There is a variation to the output handshake protocol that allows three-state operation of Port C. It is possible to directly interconnect this 8-bit parallel port to other 8-bit three-state devices with no additional external parts. The STRA signal is used as an acknowledge/enable input whose sense is controlled by the EGA bit in the PIOC register. The EGA bit specifies the transition from the asserted to the deasserted state of the STRA Input signal. If EGA is zero, the asserted state is high and falling edges are interpreted as acknowledge signals. If EGA is one, the asserted state is low and rising edges are interpreted as acknowledge signals. As long as the STRA input pin is negated, all Port C bits obey the data direction specified by DDRC. Bits which are configured as inputs (DDR bit equals zero) will be high impedance. When the STRA |
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