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INDUSTRIALTEMPERATURERANGE

IDT5V995

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate

requirements for special timing relationships between clocked compo-

from 625ps to 1.3ns (see Programmable Skew Range and Resolution

Table). There are nine skew configurations available for each output

to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)

are used, they are intended for but not restricted to hard-wiring. Undriven

3-level inputs default to the MID level. Where programmable skew is

not a requirement, the control pins can be left open for the zero skew

default setting. The Control Summary Table shows how to select specific

PROGRAMMABLESKEW

EXTERNALFEEDBACK

By providing external feedback, the IDT5V995 gives users flexibility

with regard to skew adjustment. The FB signal is compared with the

input REF signal at the phase detector in order to drive the VCO. Phase

differences cause the VCO of the PLL to adjust upwards or downwards

accordingly.

NOTES:

1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

FS = LOW

FS = MID

FS = HIGH

Comments

24 to 50MHz

48 to 100MHz

96 to 200MHz

Max Adjustment:

±7.8125ns

±7.8125ns

±7.8125ns

ns

±67.5°

±135°

±270°

PhaseDegrees

±18.75%

±37.5%

±75%

% of Cycle Time

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PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE