CY2077
Document #: 38-07210 Rev. *B
Page 6 of 13
t2
Output Clock Rise Time
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 35 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 10 pF
Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 35 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 20 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 10 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t3
Output Clock Fall Time
Between 0.8V – 2.0V, VDD = 4.5V – 5.5V, CL = 35 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 10 pF
Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 35 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 20 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 10 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t4
Start-up Time Out of
Power-down
PWR_DWN pin LOW to HIGH[5]
1
2
ms
t5a
Power-down Delay Time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T= period of output clk)
T/2
T+10
ns
t5b
Power-down Delay Time
(asynchronous setting)
PWR_DWN pin LOW to output LOW
10
15
ns
t6
Power-up Time
From power on[5]
1
2
ms
t7a
Output Disable Time
(synchronous setting)
OE pin LOW to output high-Z
(T= period of output clk)
T/2
T + 10
ns
t7b
Output Disable Time
(asynchronous setting)
OE pin LOW to output high-Z
10
15
ns
t8
Output Enable Time
(always synchronous
enable)
OE pin LOW to HIGH
(T = period of output clk)
T
1.5T +
25ns
ns
t9
Peak-to-Peak Period
Jitter
VDD = 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, VCO > 100 MHz
VDD = 3.0V – 5.5V, Fo < 33 MHz
80
0.3%
150
1%
ps
% of
FO
Switching Waveforms
Output Clock Switching Characteristics Industrial Over the Operating Range[4]
Parameter
Description
Test Conditions
Min. Typ.
Max. Unit
Duty Cycle Timing (t1w, t1x, t1y)
t1A
t1B
OUTPUT
Output Rise/Fall Time
OUTPUT
t2
VDD
0V
t3
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