10 / 21 page
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 10 of 21
Capacitance[18]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 1.5V
5pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7
pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[19]
Cypress
Parameter
Consortium
Parameter
Description
167 MHz
133 MHz
100 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPower
[20]
VCC (typical) to the First Access Read or Write
10
10
10
µs
Cycle Time
tCYC
tKHKH
K Clock and C Clock Cycle Time
6.0
7.5
10.0
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
2.4
3.2
3.5
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
2.4
3.2
3.5
ns
tKHKH
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to C/C
Rise (rising edge to rising edge)
2.7
3.3
3.4
4.1
4.4
5.4
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to
rising edge)
0.0
2.0
0.0
2.5
0.0
3.0
ns
Set-up Times
tSA
tSA
Address Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
tSC
tSC
Control Set-up to Clock (K and K) Rise (RPS,
WPS, BWS0, BWS1)
0.7
0.8
1.0
ns
tSD
tSD
D[x:0] Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
Hold Times
tHA
tHA
Address Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
tHC
tHC
Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS0, BWS1)
0.7
0.8
1.0
ns
tHD
tHD
D[x:0] Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid[21]
2.5
3.0
3.0
ns
Note:
18. Tested initially and after any design or process change that may affect these parameters.
1.25V
0.25V
R = 50
Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
RL = 50Ω
Z0 = 50Ω
VREF = 0.75V
VDDQ/2
[18]
0.75V
Under
Test
VDDQ/2
Device
Under
Test
OUTPUT
VDDQ/2
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
RQ =
250
Ω
(b)
RQ=
250
Ω
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
