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SCAN921260UJB Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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SCAN921260UJB Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 16 page Application Information (Continued) BIST Alone Mode Selection BIST_ACT BIST_SEL2 BIST_SEL1 BIST_SEL0 BIST for Channel 1 000 0 1 001 1 1 010 2 1 011 3 1 100 4 1 101 5 1 1 1 0 All Channels 1 1 1 1 IDLE 0 X X X IDLE POWER CONSIDERATIONS An all CMOS design of the Deserializer makes it an inher- ently low power device. POWERING UP THE DESERIALIZER The SCAN921260 can be powered up at any time by follow- ing the proper sequence. The REFCLK input can be running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the De- serializer detects data transmission at its inputs and locks to the incoming data stream. TRANSMITTING DATA Once you power up the Deserializer, it must be phase locked to the transmitter to transmit data. Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to one of the SYNC inputs of the Serializer will guarantee that enough SYNC patterns are sent to achieve Deserializer lock. The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock” circuitry to find and lock to the data stream. While the Deserializer LOCKn output is low, data at the Deserializer outputs (ROUT0-9) are valid, except for the specific case of loss of lock during transmission which is further discussed in the "Recovering from LOCK Loss" sec- tion below. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably receive data. Various environmental and systematic factors include: Serializer: TCLK jitter, V CC noise (noise bandwidth and out-of-band noise) Media: ISI, Large V CM shifts Deserializer: V CC noise RECOVERING FROM LOCK LOSS In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. There- fore, after the Deserializer relocks to the incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be suspect for bit errors. The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as described above, or by random locking, which can take more time, depending on the data patterns being received. HOT INSERTION All the BusLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 10. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the SCAN921260 should be designed to provide noise-free power to the de- vice. Good layout practice will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. There are a few common practices which should be followed when designing PCB’s for Bus LVDS Signaling. Recommended layout prac- tices are: • Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals). Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. • Keep Serializers and Deserializers as close to the (Bus LVDS port side) connector as possible. Longer stubs lower the impedance of the bus, increase the load on the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity. www.national.com 10 |
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