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SCAN921260UJB Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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SCAN921260UJB Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 16 page Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified(Note 2) (Continued) Symbol Parameter Conditions Min Typ Max Units Timing Requirements for REFCLK t RFCP REFCLK Period 15.15 50 ns t RFDC REFCLK Duty Cycle 40 50 60 % t RFCP/tTCP Ratio of REFCLK to TCLK 0.95 1.05 t RFTT REFCLK Transition Time 8ns Deserializer Switching Characteristics t RCP RCLK Period RCLK 15.15 50 ns t RDC RCLK Duty Cycle RCLK (Note 7) 45 50 55 % t CHTST Period of Bus LVDS signal when CHTST is selected by MUX CHTST (Note 6) 25 ns t CLH CMOS/TTL Low-to-High Transition Time C L = 15pF 1.7 6 ns t CHL CMOS/TTL High-to-Low Transition Time C L = 15pF 1.6 6 ns t ROS Rout Data Valid before RCLK C L = 15pF, Figure 2 0.35*t RCP ns t ROH Rout Data Valid after RCLK C L = 15pF, Figure 2 -0.35*t RCP ns t HZR High to TRI-STATE Delay C L = 15pF, Figure 7 12 ns t LZR Low to TRI-STATE Delay 12 ns t ZHR TRI-STATE to High Delay 12 ns t ZLR TRI-STATE to Low Delay 12 ns t DD Deserializer Delay Figure 1 1.75*t RCP +3 1.75*t RCP +7 1.75*t RCP +10.5 ns t DSR1 Deserializer PLL LOCK Time from PWRDN (with SYNCPAT) Figure 3 (Note 4) 66Mhz 2 us 20Mhz 10 us t DSR2 Deserializer PLL Lock Time from SYNCPAT Figure 4 (Note 4) 66Mhz 1.5 us 20Mhz 5 us t RNMI-R Ideal Strobe Window Right 66Mhz, Figure 10 +400 ps t RNMI-L Ideal Strobe Window Left 66Mhz, Figure 10 -400 ps Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for Vcc = 3.3V and TA =25˚C Note 3: Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltage are referenced to ground except VOD, VTH and VTL which are differential voltages. Note 4: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions of the incoming data stream (SYNCPATs). tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI−) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data. Note 5: tRNM is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise Margin is Guaranteed By Design (GBD) using statistical analysis. Note 6: Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate. Note 7: Guaranteed By Design (GBD) using statistical analysis. www.national.com 3 |
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