PM39LV020-70JCE datasheet(6/20 Pages) PMC

Part #	PM39LV020-70JCE

Description	512 Kbit / 1Mbit / 2Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory

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Manufacturer	PMC [PMC-Sierra, Inc]

Direct Link	http://www.pmc-sierra.com

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Programmable Microelectronics Corp.

Issue Date: December, 2003 Rev: 1.2

PMC

Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040

6

DEVICE OPERATION (CONTINUED)

CHIP ERASE

The entire memory array can be erased through a chip

erase operation. Pre-programs the devices are not

required prior to a chip erase operation. Chip erase starts

immediately after a six-bus-cycle chip erase command

sequence. All commands will be ignored once the chip

erase operation has started. The devices will return to

standby mode after the completion of chip erase.

SECTOR AND BLOCK ERASE

The memory array of Pm39LV512/010/020/040 are or-

ganized into uniform 4 Kbyte sectors. A sector erase

operation allows to erase any individual sector without

affecting the data in others. The memory array of

Pm39LV010/020/040, excluding Pm39LV512, are also

organized into uniform 64 Kbyte blocks (sector group -

consists of sixteen adjacent sectors). A block erase

operation allows to erase any individual block. The sec-

tor or block erase operation is similar to chip erase.

I/O7 DATA# POLLING

The Pm39LV512/010/020/040 provide a Data# Polling

feature to indicate the progress or completion of a pro-

gram and erase cycles. During a program cycle, an at-

tempt to read the devices will result in the complement

of the last loaded data on I/O7. Once the program op-

eration is completed, the true data of the last loaded

data is valid on all outputs. During a sector, block, or

chip erase cycle, an attempt to read the device will re-

sult a “0” on I/O7. After the erase operation is completed,

an attempt to read the device will result a “1” on I/O7.

I/O6 TOGGLE BIT

The Pm39LV512/010/020/040 also provide a Toggle Bit

feature to detect the progress or completion of a pro-

gram and erase cycles. During a program or erase cycle,

an attempt to read data from the device will result a

toggling between “1” and “0” on I/O6. When the program

or erase operation is complete, I/O6 will stop toggling

and valid data will be read. Toggle bit may be accessed

at any time during a program or erase cycle.

HARDWARE DATA PROTECTION

Hardware data protection protects the devices from un-

intentional erase or program operation. It is performed

in the following ways: (a) VCC sense: if VCC is below 1.8

V (typical), the write operation is inhibited. (b) Write in-

hibit: holding any of the signal OE# low, CE# high, or

WE# high inhibits a write cycle. (c) Noise filter: pulses

of less than 5 ns (typical) on the WE# or CE# input will

not initiate a write operation.

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Table 1. Product Identification

Similar Part No. - PM39LV020-70JCE

Manufacturer	Part #	Datasheet	Description
Artesyn Technologies	PM390	39Kb / 2P	Single, dual and triple output 2.5 to 15 Watt AC/DC encapsulated modules
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	PM390K	39Kb / 2P	Single, dual and triple output 2.5 to 15 Watt AC/DC encapsulated modules
	PM391	39Kb / 2P	Single, dual and triple output 2.5 to 15 Watt AC/DC encapsulated modules
	PM391CE	46Kb / 2P	Single, dual and triple output 2.5 to 15 Watt AC/DC encapsulated modules

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PM39LV020-70JCE Datasheet(PDF) 6 Page - PMC-Sierra, Inc

PM39LV020-70JCE Datasheet(HTML) 6 Page - PMC-Sierra, Inc

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