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NID9N05CL Datasheet(PDF) 1 Page - ON Semiconductor |
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NID9N05CL Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2004 July, 2004 − Rev. 5 1 Publication Order Number: NID9N05CL/D NID9N05CL Power MOSFET 9.0 A, 52 V, N−Channel, Logic Level, Clamped MOSFET w/ ESD Protection in a DPAK Package Benefits • High Energy Capability for Inductive Loads • Low Switching Noise Generation Features • Diode Clamp Between Gate and Source • ESD Protection − HBM 5000 V • Active Over−Voltage Gate to Drain Clamp • Scalable to Lower or Higher R DS(on) • Internal Series Gate Resistance Applications • Automotive and Industrial Markets: Solenoid Drivers, Lamp Drivers, Small Motor Drivers MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage Internally Clamped VDSS 52−59 V Gate−to−Source Voltage − Continuous VGS ±15 V Drain Current − Continuous @ TA = 25°C Drain Current − Single Pulse (tp = 10 ms) ID IDM 9.0 35 A Total Power Dissipation @ TA = 25°C PD 28.8 W Operating and Storage Temperature Range TJ, Tstg −55 to 175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 125°C (VDD = 50 V, ID(pk) = 1.5 A, VGS = 10 V, RG = 25 W) EAS 160 mJ Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) RqJC RqJA RqJA 5.2 72 100 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8 ″ from Case for 10 s TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 ″ pad size, (Cu area 1.127 in2) 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu area 0.412 in2) Device Package Shipping† ORDERING INFORMATION NID9N05CLT4 DPAK 2500/Tape & Reel DPAK CASE 369C STYLE 2 MPWR Drain (Pins 2, 4) Source (Pin 3) Gate (Pin 1) MARKING DIAGRAM D9N05CL = Device Code A = Assembly Location Y = Year WW = Work Week RG Overvoltage Protection ESD Protection http://onsemi.com 1 = Gate 2 = Drain 3 = Source 4 = Drain 1 2 3 4 NID9N05CL DPAK 75 Units/Rail AYWW D9N05CL VDSS (Clamped) RDS(ON) TYP ID MAX (Limited) 52 V 90 m Ω 9.0 A †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. |
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