8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

_______________________________________________________________________________________

5

Note 1:

Note 2:

All channel performance is guaranteed by correlation to a single channel test.

Note 3:

Offset nulled.

Note 4:

The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:

Note 5:

Throughput section for more information.

Note 6:

All analog inputs are driven with an FS 100kHz sine wave.

I

VV

R

CH

CH

BIAS

CH

_

_

_

=

−

TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Internal clock

1.6

1.8

µs

Time-to-First-Conversion Result

External clock, Figure 6

16

Clock

cycles

Internal clock

0.3

0.36

µs

Time-to-Next-Conversion Result

External clock, Figure 6

3

Clock

cycles

CONVST Pulse-Width Low

(Acquisition Time)

(Note 9)

0.16

100

µs

CS Pulse Width

30

ns

RD Pulse-Width Low

30

ns

RD Pulse-Width High

30

ns

WR Pulse-Width Low

30

ns

CS to WR

(Note 10)

ns

WR to CS

(Note 10)

ns

CS to RD

(Note 10)

ns

RD to CS

(Note 10)

ns

Data-Access Time

(RD Low to Valid Data)

30

ns

Bus-Relinquish Time (RD High)

30

ns

Internal clock

80

ns

EOC Pulse Width

External clock, Figure 6

1

Clock

cycles

Input-Data Setup Time

10

ns

Input-Data Hold Time

10

ns

External-Clock Period

0.08

10.00

µs

External-Clock High Period

Logic sensitive to rising edges

20

ns

External-Clock Low Period

Logic sensitive to rising edges

20

ns

External-Clock Frequency

(Note 11)

0.1

12.5

MHz

Internal-Clock Frequency

10

MHz

CONVST High to CLK Edge

20

(Note 12)

ns

EOC Low to RD

0ns