DECEMBER 2002

DSC-5298/03

1

©2002 Integrated Device Technology, Inc.

Pin Description Summary

cycle, and on the next clock cycle the associated data cycle occurs, be it

read or write.

The IDT71V65703/5903 contain address, data-in and control signal

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

A Clock Enable (

CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CENishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.

There are three chip enable pins (

user to deselect the device when desired. If any one of these three is not

assertedwhenADV/

LDislow,nonewmemoryoperationcanbeinitiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write

isinitiated.

The IDT71V65703/5903 have an on-chip burst counter. In the burst

mode, the IDT71V65703/5903 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/

LD signal is used to load a new

externaladdress(ADV/

LD=LOW)orincrementtheinternalburstcounter

(ADV/

LD = HIGH).

The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-

pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

Features

x

x

x

x

x

256K x 36, 512K x 18 memory configurations

x

x

x

x

x

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

x

x

x

x

x

cycles

x

x

x

x

x

Internally synchronized output buffer enable eliminates the

need to control

OE

x

x

x

x

x

Single R/

W (READ/WRITE) control pin

x

x

x

x

x

4-word burst capability (Interleaved or linear)

x

x

x

x

x

Individual byte write (

x

x

x

x

x

Three chip enables for simple depth expansion

x

x

x

x

x

3.3V power supply (±5%)

x

x

x

x

x

x

x

x

x

x

Power down controlled by ZZ input

x

x

x

x

x

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

around between reads and writes, or writes and reads. Thus they have

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

Address Inputs

Input

Synchronous

Chip Enables

Input

Synchronous

OE

Output Enable

Input

Asynchronous

R/

W

Read/Write Signal

Input

Synchronous

CEN

Clock Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/

LD

Advance Burst Address/Load New Address

Input

Synchronous

LBO

Linear/Interleaved Burst Order

Input

Static

ZZ

Sleep Mode

Input

Asynchronous

Data Input/Output

I/O

Synchronous

Core Power, I/O Power

Supply

Static

Ground

Supply

Static

5298 tbl 01

IDT71V65703

IDT71V65903

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.