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IDT71V65703S80BG Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT71V65703S80BG Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 26 page  6.42 8 IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Pin Configuration 256K x 36, 165 fBGA Pin Configuration 512K x 18, 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC(3) A7 CE1 BW3 BW2 CE2 CEN ADV /LD A17 A8 NC B NC A6 CE2 BW4 BW1 CLK R/ W OE NC(3) A9 NC(3) C I/OP3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2 D I/O17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14 E I/O19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12 F I/O21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10 G I/O23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9 I/O8 H VSS(1) VDD(2) NC VDD VSS VSS VSS VDD NC NC ZZ J I/O25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7 I/O6 K I/O27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5 I/O4 L I/O29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3 I/O2 M I/O31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1 I/O0 N I/OP4 NC VDDQ VSS DNU(4) NC VSS(1) VSS VDDQ NC I/OP1 P NC NC(3) A5 A2 DNU(4) A1 DNU(4) A10 A13 A14 NC R LBO NC(3) A4 A3 DNU(4) A0 DNU(4) A11 A12 A15 A16 5298 tbl 25a 1 234 567 89 10 11 ANC(3) A7 CE1 BW2 NC CE2 CEN ADV /LD A18 A8 A10 BNC A6 CE2 NC BW1 CLK R/ W OE NC(3) A9 NC(3) CNC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1 DNC I/O8 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7 ENC I/O9 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6 FNC I/O10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5 GNC I/O11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4 HVSS(1) VDD(2) NC VDD VSS VSS VSS VDD NC NC ZZ JI/O12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3 NC KI/O13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2 NC LI/O14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1 NC MI/O15 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O0 NC NI/OP2 NC VDDQ VSS DNU(4) NC VSS(1) VSS VDDQ NC NC PNC NC(3) A5 A2 DNU(4) A1 DNU(4) A11 A14 A15 NC R LBO NC(3) A4 A3 DNU(4) A0 DNU(4) A12 A13 A16 A17 5298 tbl25b NOTES: 1. Pins H1 and N7 do not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is > VIH. 3. Pin B9, B11, A1, R2 and P2 are reserved for a future 18M, 36M, 72M, 144M and 288M respectively. 4. DNU = Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD). |
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