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IDT70V9349L6PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V9349L6PF Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 16 page  ©2003 Integrated Device Technology, Inc. AUGUST 2003 DSC-5638/3 1 Functional Block Diagram Features: ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 6.5/7.5/9ns (max.) – Industrial: 7.5ns (max.) ◆ Low-power operation – IDT70V9359/49L Active: 450mW (typ.) Standby: 1.5mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via the FT/PIPE pins ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 3.5ns setup to clock and 0ns hold on all control, data, and addressinputs – Data input, address, and control registers – Fast 6.5ns clock to data out in the Pipelined output mode – Self-timedwriteallowsfastcycletime – 10ns cycle time, 100MHz operation in Pipelined output mode ◆ Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ◆ LVTTL- compatible, single 3.3V (±0.3V) power supply ◆ Industrial temperature range (–40°C to +85°C) is available for 83 MHz ◆ Available in a 100-pin Thin Quad Flatpack (TQFP) and 100- pin Fine Pitch Ball Grid Array (fpBGA) packages. IDT70V9359/49L 0a 1a 0b 1b 0/1 ab I/O Control 1 0/1 0 FT/PIPER R/WR UBR LBR CE0R OER CE1R MEMORY ARRAY Counter/ Address Reg. 5638 drw 01 A12R(1) A0R CLKR ADSR CNTENR CNTRSTR I/O9L-I/O17L I/O0L-I/O8L I/O9R-I/O17R I/O0R-I/O8R A0L CLKL ADSL A12L(1) CNTENL CNTRSTL Counter/ Address Reg. R/WL UBL LBL CE0L OEL CE1L 1 0/1 0 1b 0b 1a 0a 0/1 ba I/O Control FT/PIPEL HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM NOTE: 1. A12 is a NC for IDT70V9349. |
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