CY7C1648KV18 datasheet(14/29 Pages) CYPRESS

Part #	CY7C1648KV18

Description	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

Download	29 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

14 / 29 page

Document Number: 001-44061 Rev. *L

Page 14 of 29

CY7C1648KV18

CY7C1650KV18

TAP AC Switching Characteristics

Over the Operating Range

Parameter [16, 17]

Description

Min

Max

Unit

tTCYC

TCK clock cycle time

50

–

ns

tTF

TCK clock frequency

–

20

MHz

tTH

TCK clock high

20

–

ns

tTL

TCK clock low

20

–

ns

Setup Times

tTMSS

TMS setup to TCK clock rise

5

–

ns

tTDIS

TDI setup to TCK clock rise

5

–

ns

tCS

Capture setup to TCK rise

5

–

ns

Hold Times

tTMSH

TMS hold after TCK clock rise

5

–

ns

tTDIH

TDI hold after clock rise

5

–

ns

tCH

Capture hold after clock rise

5

–

ns

Output Times

tTDOV

TCK clock low to TDO valid

–

10

ns

tTDOX

TCK clock low to TDO invalid

0

–

ns

Notes

16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Similar Part No. - CY7C1648KV18

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1648KV18-400BZXC	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

More results

Similar Description - CY7C1648KV18

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1668KV18	771Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1548KV18	844Kb / 29P	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C2670KV18	824Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Renesas Technology Corp	R1QHA4436RBG	916Kb / 30P	144-Mbit DDR?줚I SRAM 2-word Burst Architecture (2.0 Cycle Read latency)
Cypress Semiconductor	CY7C2644KV18	840Kb / 30P	144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
	CY7C1643KV18	861Kb / 31P	144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C2642KV18	885Kb / 30P	144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
	CY7C1166KV18	874Kb / 29P	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1546KV18	959Kb / 31P	72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

More results

CY7C1648KV18 Datasheet(PDF) 14 Page - Cypress Semiconductor

CY7C1648KV18 Datasheet(HTML) 14 Page - Cypress Semiconductor

Similar Part No. - CY7C1648KV18

Similar Description - CY7C1648KV18

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL