CY7C1618KV18 datasheet(17/32 Pages) CYPRESS

Part #	CY7C1618KV18

Description	144-Mbit DDR II SRAM Two-Word Burst Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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17 / 32 page

Document Number: 001-44274 Rev. *N

Page 17 of 32

CY7C1618KV18/CY7C1620KV18

TAP Timing and Test Conditions

Figure 3 shows the TAP timing and test conditions. [18]

Figure 3. TAP Timing and Test Conditions

tTL

tTH

(a)

TDO

CL = 20 pF

Z0 = 50

GND

0.9 V

50



1.8 V

0 V

ALL INPUT PULSES

0.9 V

Test Clock

Test Mode Select

TCK

TMS

Test Data In

TDI

Test Data Out

tTCYC

tTMSH

tTMSS

tTDIS

tTDIH

tTDOV

tTDOX

TDO

Note

18. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

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CY7C1618KV18 Datasheet(PDF) 17 Page - Cypress Semiconductor

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