AFE8201

SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005

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9

The read cycle is illustrated in Figure 7. It is similar to the write cycle, except that instead of the data word being

clocked into MOSI during the second half of the cycle, the data word is clocked out of MISO. The two data read

instructions are similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9.

SCK

CS_N

MOSI

MSB

LSB

MSB

LSB

MISO

Instruction

Data

Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory

0

1

0

REG_ADDR

Don’t Care

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 8. Register Read Instruction Format

011

MEM_ADDR

MEM

Don’t Care

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 9. Memory Read Instruction Format

Block transfers are supported for memory reading and writing. Multiple data words are transmitted following the

memory read or write instruction for a block transfer. The data words are sequentially read from or written to RAM

sequentially starting at the address contained in the instruction. The sequential RAM access terminates when the

CS_N line goes high. Figure 10 shows a memory block read cycle. In the illustration, three successive memory

locations are read starting at address N. The memory block write cycle is similar, except of course data is clocked

into MOSI.

SCK

CS_N

MSB

LSB

MSB

LSB

MISO

Instruction

Data (N)

Data (N + 1)

Data (N + 2)

Figure 10. Block Memory Read Cycle Control Interface

In all cases, the control interface is reset when CS_N goes high. If the final SCK is not received before CS_N goes

high, then the cycle will end prematurely. For a read cycle, transfer of data will terminate; for a write cycle, no data

will be written to register or memory.