ADN2819ACPZ-CML-RL1 datasheet(5/24 Pages) AD

Part #	ADN2819ACPZ-CML-RL1

Description	Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

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ADN2819

Rev. B | Page 5 of 24

Parameter

Conditions

Min

Typ

Max

Unit

Setup Time

TS (See Figure 3)

OC-48

140

ps

GbE

350

ps

OC-12

750

ps

OC-3

3145

ps

Hold Time

TH (See Figure 3)

OC-48

150

ps

GbE

350

ps

OC-12

750

ps

OC-3

3150

ps

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range

@ REFCLKP or REFCLKN

0

VCC

V

Peak-to-Peak Differential Input

100

mV

Common-Mode Level

DC-coupled, single-ended

VCC/2

V

TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N)

CML inputs

Peak-to-Peak Differential Input Voltage

0.8

V

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage

VIH

2.0

V

Input Low Voltage

VIL

0.8

V

Input Current

VIN = 0.4 V or VIN = 2.4 V

–5

+5

µA

Input Current (SEL0 and SEL1 Only)5

VIN = 0.4 V or VIN = 2.4 V

–5

+50

µA

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage

VOH, IOH = –2.0 mA

2.4

V

Output Low Voltage

VOL, IOL = +2.0 mA

0.4

V

1 PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

2 PWD measurement made on quantizer outputs in bypass mode.

3 Jitter tolerance measurements are equipment limited.

4 TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

5 SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.

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ADN2819ACPZ-CML-RL1 Datasheet(PDF) 5 Page - Analog Devices

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