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ADN2819ACPZ-CML1 Datasheet(PDF) 1 Page - Analog Devices |
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ADN2819ACPZ-CML1 Datasheet(HTML) 1 Page - Analog Devices |
1 / 24 page Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for all rates, including 15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK LVPECL/LVDS/LVCMOS/LVTTL compatible inputs (LVPECL/LVDS only at 155.52 MHz) 19.44 MHz oscillator on-chip to be used with external crystal Loss of lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation: 3.3 V Low power: 540 mW typical 7 mm × 7 mm 48-lead LFCSP APPLICATIONS SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14 FEC rates WDM transponders Regenerators/repeaters Test equipment Backplane applications PRODUCT DESCRIPTION The ADN2819 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for –40°C to +85°C ambient temperature, unless otherwise noted. The device is intended for WDM system applications, and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both native rates and 15/14 rate digital wrappers are supported by the ADN2819, without any change of reference clock. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2819 is available in a compact 7 mm × 7 mm, 48-lead chip scale package. FUNCTIONAL BLOCK DIAGRAM LEVEL DETECT DATA RETIMING DIVIDER 1/2/4/16 FRACTIONAL DIVIDER FREQUENCY LOCK DETECTOR LOOP FILTER PHASE SHIFTER PHASE DET. VCO XTAL OSC LOOP FILTER QUANTIZER /n ADN2819 SLICEP/N VCC VEE CF1 CF2 LOL REFSEL[0..1] REFCLKP/N XO1 XO2 REFSEL SEL[0..2] CLKOUTP/N DATAOUTP/N SDOUT THRADJ VREF NIN PIN 2 2 2 2 2 3 Figure 1. |
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