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ZL50117GAG Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc |
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ZL50117GAG Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc |
2 / 95 page ZL50115/16/17/18/19/20 Data Sheet 2 Zarlink Semiconductor Inc. System Interfaces • Flexible 32 bit Motorola host interface • On-chip packet memory with jitter buffer compensation for over 128 ms of packet delay variation Packet Processing Functions • Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable • Packet re-sequencing to allow lost packet detection and re-ordering • Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues • Programmable classification of incoming packets at layers 2 through 5 • Wire speed processing of all packets regardless of classification providing low latency • Supports up to 128 separate CESoP connections across the Packet Switched Network Applications • Circuit Emulation Services over Packet Networks • Leased Line support over packet networks • TDM over Cable • TDM over WiFi (802.11x) • TDM over WiMAX (802.16) • Fibre To The Premises G/E-PON • Layer 2 VPN services • Customer-premise and Provider Edge Routers and Switches • Ethernet and IP based IADs |
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