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SN74AUP1G00 Datasheet(PDF) 2 Page - Texas Instruments

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Part No. SN74AUP1G00
Description  LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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 2 page
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SN74AUP1G00
LOW POWER SINGLE 2INPUT POSITIVENAND GATE
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
NanoStar
 − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
SN74AUP1G00YEPR
_ _ _HA_
−40
°C to 85°C
NanoFree
 − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel
SN74AUP1G00YZPR
_ _ _HA_
−40
°C to 85°C
SOT (SOT-23) − DBV
Tape and reel
SN74AUP1G00DBVR
H00_
SOT (SC-70) − DCK
Tape and reel
SN74AUP1G00DCKR
HA_
SOT (SOT-533) − DRL
Reel or 4000
SN74AUPG00DRLR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
= Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
A
B
OUTPUT
Y
L
L
H
L
HH
H
LH
H
H
L
logic diagram (positive logic)
1
A
2
B
Y
4




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