16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

10

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Pin Description (continued)

PIN

NAME

FUNCTION

40

PD

Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.

Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.

41

XORN

Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow

the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the

42

XORP

LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to

pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If

unused, connect XORP to GND.

43

SELIQP

LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs.

Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.

44

SELIQN

Complementary LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the

I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.

45

B15P

Data Bit 15 (MSB)

46

B15N

Complementary Data Bit 15 (MSB)

47

B14P

Data Bit 14

48

B14N

Complementary Data Bit 14

49

B13P

Data Bit 13

50

B13N

Complementary Data Bit 13

51

B12P

Data Bit 12

52

B12N

Complementary Data Bit 12

53

B11P

Data Bit 11

54

B11N

Complementary Data Bit 11

55

B10P

Data Bit 10

56

B10N

Complementary Data Bit 10

57

B9P

Data Bit 9

58

B9N

Complementary Data Bit 9

59

B8P

Data Bit 8

60

B8N

Complementary Data Bit 8

61

Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF

capacitor to GND.

62

B7P

Data Bit 7

63

B7N

Complementary Data Bit 7

64

B6P

Data Bit 6

65

B6N

Complementary Data Bit 6

66

B5P

Data Bit 5

67

B5N

Complementary Data Bit 5

68

B4P

Data Bit 4

—EP

Exposed Pad. Must be connected to GND through a low-impedance path.