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LMX2505LQ1321 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LMX2505LQ1321 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 16 page Functional Description (Continued) HIGH SPEED LOCK-UP MODE Two frequency-locking modes are provided: a Normal mode and a High Speed mode for faster lock times. The HS bit in register R0 controls the locking mode. TABLE 5. Lock-up Modes HS Bit Mode 0 Normal mode 1 High Speed mode MICROWIRE INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The interface is comprised of three signal pins: CLK, DATA, and LE (Latch Enable). Serial data is clocked into the 24-bit shift register on the rising edge of the clock. The last bits decode the internal control register address. When the latch enable (LE) transitions from LOW to HIGH, data stored in the shift registers is loaded into the corresponding control register. The data is loaded MSB first. 20067109 FIGURE 3. Lock Detect Flow Diagram www.national.com 10 |
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