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ICS84330BVT Datasheet(PDF) 11 Page - Integrated Circuit Systems |
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ICS84330BVT Datasheet(HTML) 11 Page - Integrated Circuit Systems |
11 / 19 page 84330BV www.icst.com/products/hiperclocks.html REV. B JULY 26, 2004 11 Integrated Circuit Systems, Inc. ICS84330 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 6B. PCB BOARD LAYOUT FOR ICS84330 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C3 and C4, as close as pos- sible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The differential 50 Ω output traces should have the same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic in- ductance and capacitance. Other signal traces should not be routed near the crystal traces. R7 Signals Traces VCCA C1 C4 VCC 50 Ohm Traces C11 C3 GND PIN 2 C2 PIN 1 C16 U1 X1 VIA VCCA |
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