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K4S511633F-YPC Datasheet(PDF) 1 Page - Samsung semiconductor |
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K4S511633F-YPC Datasheet(HTML) 1 Page - Samsung semiconductor |
1 / 12 page K4S511633F-Y(P)C/L/F September 2004 1 Mobile-SDRAM • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25 °C ~ 70°C). • 1 /CS Support. • 2Chips DDP 54Balls FBGA ( -YXXX -Pb, -PXXX -Pb Free). FEATURES The K4S511633F is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. GENERAL DESCRIPTION ORDERING INFORMATION - Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25 °C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Part No. Max Freq. Interface Package K4S511633F-Y(P)C/L/F75 133MHz(CL3), 111MHz(CL2) LVCMOS 54 FBGA Pb (Pb Free) K4S511633F-Y(P)C/L/F1H 111MHz(CL2) K4S511633F-Y(P)C/L/F1L 111MHz(CL=3)*1, 83MHz(CL2) 8M x 16Bit x 4 Banks Mobile SDRAM Address configuration Organization Bank Row Column Address 32M x16 BA0,BA1 A0 - A12 A0 - A9 |
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