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M38C35EAAXXXFP Datasheet(PDF) 11 Page - Mitsubishi Electric Semiconductor |
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M38C35EAAXXXFP Datasheet(HTML) 11 Page - Mitsubishi Electric Semiconductor |
11 / 62 page 11 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C3 Group Pin P40/SCLK2 P41/T1OUT P42/T3OUT P43/ φ P44/SIN P45/SOUT P46/SCLK1 P47/SRDY P50/TAOUT P51 P52/PWM1 P53/CNTR0 P54/CNTR1 P55/INT0 P56/INT1 P57/INT2 P60/AN0 – P67/AN7 P70/XCIN P71/XCOUT P80 – P87 COM0 – COM3 Name Port P4 Port P5 Port P6 Port P7 Port P8 Common Input/Output Input/Output, individual bits Input/Output, individual bits Input Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Output I/O format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output Non-port function Serial I/O function I/O Timer output Timer output φ clock output Serial I/O function I/O Timer A output PWM output External count I/O External interrupt in- put A-D converter input Sub-clock generating circuit I/O Key input (key-on wake-up) interrupt in- put Related SFRs Serial I/O control registers 1, 2 PULL register B Timer 12 mode register PULL register B Timer 34 mode register PULL register B φ output control register PULL register B Serial I/O control registers 1, 2 PULL register B Timer A mode register Timer A control reigster PULL register B Timer 56 mode register PULL register B Interrupt edge selection reg- ister PULL register B Interrupt edge selection reg- ister PULL register B A-D control register PULL register B CPU mode register PULL register A Interrupt control register 2 PULL register A LCD mode register Ref. No. (3) (4) (4) (5) (6) (7) (8) (9) (10) (11) (4) (12) (12) (13) (14) (15) (17) (16) Table 5 List of I/O port function (2) Notes 1: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. 2: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double function ports as function I/O ports, refer to the applicable sections. |
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