6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

11

NOTES:

1. R/

W or CE or UB & LB must be high during all address transitions.

UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.

CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the

CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

6. Timing depends on which enable signal is asserted last,

CE, R/W or byte control.

7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output

Test Load (Figure 2).

8. If

9. To access SRAM,

R/

W

(2)

OE

ADDRESS

(6)

(4)

(4)

(7)

2911 drw 08

(9)

(7)

(3)

2911 drw 09

ADDRESS

R/

W

(3)

(2)

(6)

(9)

(9)