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AT49LH00B4-33TC Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT49LH00B4-33TC Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 36 page  7 AT49LH00B4 3379B–FLASH–9/03 FWH/LAD[3:0] PINS: The FWH/LAD[3:0] signal lines communicate address, control, and data information over the LPC bus between a master and a peripheral. The information communi- cated are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), transfer direction (read/write), address, data, wait states, DMA channel, and bus master grant. FWH Memory Cycles A valid FWH memory cycle begins with the host driving the FWH4/LFRAME signal low for one or more clock cycles. While the FWH4/LFRAME signal is low, a valid START value of either 1101b (FWH memory read) or 1110b (FWH memory write) must be driven on the FWH/LAD[3:0] pins. Following the START field, an IDSEL (Device Select) field must be sent to the device. The IDSEL field acts like a chip select in that it indicates which device should respond to the current operation. After the IDSEL field has been sent, the 7-clock MADDR (Memory Address) field must be sent to the device to provide the 28-bit starting address loca- tion of where to begin reading or writing in the memory. Following the MADDR field, the MSIZE (Memory Size) field must be sent to indicate the number of bytes to transfer. Figure 1. FWH Memory Cycle Initiation and Addressing START FIELD: This 1-clock field indicates the start of a cycle. It is valid on the last clock that FWH4/LFRAME is sampled low. The two start fields that are used for a FWH cycle are: 1101b to indicate a FWH memory read cycle and 1110b to indicate a FWH memory write cycle. If the start field that is sampled is not one of these values, then the cycle attempted is not a FWH memory cycle. It may be a valid LPC memory cycle that the device will attempt to decode. IDSEL (DEVICE SELECT) FIELD: This 1-clock field is used to indicate which FWH compo- nent in the system is being selected. The four bits transmitted over FWH/LAD[3:0] during this clock are compared with values strapped on the ID[3:0] pins. If there is a match, the device will continue to decode the cycle to determine which bytes are requested on a read or which bytes to update on a write. If there isn’t a match, the device may discard the rest of the cycle and go into a standby power state. MADDR (MEMORY ADDRESS) FIELD: This is a 7-clock field that is used to provide a 28-bit (A27 - A0) memory address. This allows for provisioning of up to 256 MB per FWH memory device, for a total of a 4 GB addressable space if 16 FWH memory devices (256 MB each) were used in a system. The AT49LH00B4 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A27 - A23 and A21 - A19. Address bit A22 is used to determine whether reads or writes to the device will be directed to the memory array (A22 = 1) or to the register space (A22 = 0). Addresses are transferred to the device with the most significant nibble first. MSIZE (MEMORY SIZE) FIELD: The 1-clock MSIZE is used to indicate how many bytes of data will be transferred during a read or write. The AT49LH00B4 only supports single-byte transfers, so 0000b must be sent in this field to indicate a single-byte transfer. CLK FWH4/LFRAME FWH/LAD[3:0] START IDSEL MADDR MADDR MADDR MADDR MADDR MADDR MADDR MSIZE |
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