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AT49LH00B4 Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT49LH00B4 Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 36 page  2 AT49LH00B4 3379B–FLASH–9/03 The sectoring of the AT49LH00B4’s memory array has been optimized to meet the needs of today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space can be used more efficiently. Because certain BIOS code modules must reside in their own sectors by themselves, the wasted and unused memory space that occurred with previous generation BIOS Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional BIOS routines to be developed and added while still main- taining the same overall device density. The memory array of the AT49LH00B4 can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16- Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top (upper- most) of the device’s memory address space and can be hardware write protected by using the TBL pin. Alternatively, by using a different erase command, the memory array can be arranged into eight even erase sectors of 64-Kbyte each. The AT49LH00B4 supports two hardware interfaces: The FWH/LPC interface for In-System operations and the A/A Mux interface for programming during manufacturing. The Interface Configuration (IC) pin of the device provides the control between these two interfaces. An internal Command User Interface (CUI) serves as the control center between the device inter- faces and the internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation. Specifically designed for use in 3-volt systems, the AT49LH00B4 supports read, program, and erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required for programming and erasing. The AT49LH00B4 utilizes fixed program and erase times, independent of the number of pro- gram and erase cycles that have occurred. Therefore, the system does not need to be calibrated or correlated to the cumulative number of program and erase cycles. Block Diagram FLASH MEMORY ARRAY Y-GATING CONTROL LOGIC CLK FWH4/LFRAME FWH/LAD[3:0] R/C A[10:0] I/O[7:0] OE WE RDY/BSY ID[3:0] GPI[4:0] IC RST FWH/LPC INTERFACE A/A MUX INTERFACE Y-DECODER X-DECODER I/O BUFFERS AND LATCHES TBL WP INTERFACE CONTROL AND LOGIC INIT |
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