AD5415

Rev. 0 | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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23

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16

15

14

13

1

2

3

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5

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AD5415

TOP VIEW

(Not to Scale)

SDIN

SCLK

GND

R1A

R3A

R2_3A

R2A

CLR

R1B

R3B

R2_3B

R2B

LDAC

SDO

SYNC

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

DAC A Current Output.

2

DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to

achieve single-supply operation.

3

DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external

amplifier output.

4–7

R1A–R3A

DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with

minimum external components.

8

DAC A Reference Voltage Input Pin.

9

GND

Ground Pin.

10

LDAC

Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is

asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an

automatic or synchronous update mode is selected whereby the DAC is updated on the 16th clock falling edge

when the device is in standalone mode or on the rising edge of SYNC when in daisy-chain mode.

11

SCLK

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into

the shift register on the rising edge of SCLK.

12

SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By

default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the

user to change the active edge to the rising edge.

13

SDO

Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift

register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes

the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges

to the active clock edge.

14

SYNC

Active Low Control Input. The frame synchronization signal for the input data. When SYNC goes low, it powers on

the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active

edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched to the shift

register on the 16th active clock edge.

15

CLR

Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the

user to enable the hardware CLR pin as a clear to zero scale or midscale, as required.

16

Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

17

DAC B Reference Voltage Input Pin.

18–21

R1B–R3B

DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with

minimum of external components.

22

DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external

amplifier output.

23

DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to

achieve single-supply operation.

24

DAC B Current Output.