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24LC512 Datasheet(PDF) 8 Page - Microchip Technology |
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24LC512 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 26 page  24AA512/24LC512/24FC512 DS21754E-page 8 2004 Microchip Technology Inc. 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX512 this is set as ‘1010 ’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1 and A0). The Chip Select bits allow the use of up to eight 24XX512 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because all A15…A0 are used, there are no upper address bits that are “don’t care”. The upper address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24XX512 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010 ’ code and appro- priate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX512 will select a read or write operation. FIGURE 5-1: CONTROL BYTE FORMAT 5.1 Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 4 Mbit by adding up to eight 24XX512s on the same bus. In this case, software can use A0 of the control byte as address bit A16; A1, as address bit A17; and A2, as address bit A18. It is not possible to sequentially read across device boundaries. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS 10 1 0A2 A1 A0 S ACK R/W Control Code Chip Select Bits Slave Address Acknowledge Bit Start Bit Read/Write Bit 1 010 A 2 A 1 A 0 R/W A 11 A 10 A 9 A 7 A 0 A 8 •• • • •• A 12 CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE CONTROL CODE CHIP SELECT BITS A 13 A 14 A 15 |
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