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DS1258W-150 Datasheet(PDF) 2 Page - Dallas Semiconductor |
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DS1258W-150 Datasheet(HTML) 2 Page - Dallas Semiconductor |
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2 / 9 page  DS1258W 2 of 9 READ MODE The DS1258W executes a read cycle whenever WE (Write Enable) is inactive (high) and either/both of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable)is active (low). The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to the 16 data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CEU , CEL and OE access times are also satisfied. If CEU , CEL , and OE access times are not satisfied, then data access must be measured from the later-occurring signal, and the limiting parameter is either tCO for CEU , CEL , or tOE for OE rather than address access. WRITE MODE The DS1258W executes a write cycle whenever WE and either/both of CEU or CEL are active (low) after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CEU and/or CEL , and OE active) then WE will disable the outputs in tODW from its falling edge. READ/WRITE FUNCTION Table 1 OE WE CEL CEU VCC CURRENT DQ0-DQ7 DQ8-DQ15 CYCLE PERFORMED HH X X ICCO High-Z High-Z Output Disabled L H L L Output Output L H L H Output High-Z LH H L ICCO High-Z Output Read Cycle X L L L Input Input X L L H Input High-Z XL H L ICCO High-Z Input Write Cycle XX H H ICCS High-Z High-Z Output Disabled DATA RETENTION MODE The DS1258W provides full functional capability for VCC greater than 3.0V, and write-protects by 2.8V. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write- protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.5V, the power switching circuit |
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