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OX16PCI952-TQFP-A Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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OX16PCI952-TQFP-A Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 76 page  DataSheet Revision 1.1 Page 4 OX16PCI952 OXFORD SEMICONDUCTOR LTD. 1 PERFORMANCE COMPARISON Feature OX16PCI952 16C552 + PCI Bridge 16C652 + PCI Bridge Internal serial channels 2 0 0 Integral 1284 Compliant parallel port yes no no Multi-function PCI device yes no no Support for PCI Power Management yes no no Zero wait-state read/write operation yes no no No. of available external interrupt pins 2 2 2 DWORD access to UART Interrupt Source Registers & FIFO Levels yes no no Good-Data status yes no no Full Plug and Play with external EEPROM yes yes yes External 1x baud rate clock yes no no Max baud rate in normal mode 15 Mbps 115 Kbps 1.5 Mbps Max baud rate in 1x clock mode 60 Mbps n/a n/a FIFO depth 128 16 64 Sleep mode yes no yes Auto Xon/Xoff flow yes no yes Auto CTS#/RTS# flow yes no yes Auto DSR#/DTR# flow yes no no No. of Rx interrupt thresholds 128 4 4 No. of Tx interrupt thresholds 128 1 4 No. of flow control thresholds 128 n/a 4 Transmitter empty interrupt yes no no Readable status of flow control yes no no Readable FIFO levels yes no no Clock prescaler options 248 n/a 2 Rx/Tx disable yes no no Software reset yes no no Device ID yes no no 9-bit data frames yes no no RS485 buffer enable yes no no Infra-red (IrDA) yes no yes Table 1: OX16PCI952 performance compared with PCI Bridge + generic UART/Parallel Port Combinations. 1.1 Improvements of the OX16PCI952 over discrete solutions: Higher degree of integration: The OX16PCI952 offers two internal ultra-high performance 16C950 UARTs and one IEEE1284 compliant bi-directional parallel port. UART device driver efficiency is increased by using each channel’s features such as the 128-byte deep transmitter & receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates of each UART is up to 60Mbps. Improved access timing: Access to the internal UARTs require zero or one PCI wait states. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latency: The OX16PCI952 offers shadowed FIFO levels and Interrupt status registers of the internal UARTs, as well as general device interrupt status, to reduce the device driver interrupt latency. |
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