X40420/X40421 – Preliminary

Characteristics subject to change without notice.

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WDO

WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-

dog timer goes active.

5MR

Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-

6

RESET/

RESET

RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever

RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH when-

Ground

8

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an

open drain output and may be wire ORed with other open drain or open collector outputs. This pin

requires a pull up resistor and the input buffer is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW

and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within

the watchdog time out period results in WDO going active.

9

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

10

WP

Write Protect. WP HIGH prevents writes to any location in the device (including all the registers).

It has an internal pull down resistor. (>10M

Ω typical)

11

Battery Supply Voltage. This input provides a backup supply in the event of a failure of the

maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is

12

Output Voltage. (V)

13

BATT-ON

and current requirements are greater than 50mA.

The purpose of this output is to drive an external transistor to get higher operating currents when

to supply enough voltage and current to keep SRAM devices from losing their data–there is no

communication at this time.

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Supply Voltage

PIN DESCRIPTION (Continued)

Pin

Name

Function