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VSC8113QB2 Datasheet(PDF) 11 Page - Vitesse Semiconductor Corporation |
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VSC8113QB2 Datasheet(HTML) 11 Page - Vitesse Semiconductor Corporation |
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11 / 28 page  G52154-0, Rev 4.2 © VITESSE SEMICONDUCTOR CORPORATION Page 11 3/19/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 4: Transmit Data Input Timing Table (STS-12 Operation) Table 5: Transmit Data Input Timing Table (STS-3 Operation) Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case Figure 10: Receive Data Output Timing Diagram Table 6: Receive Data Output Timing Table (STS-12 Operation) Parameter Description Min Typ Max Units TCLKIN Transmit data input byte clock period - 12.86 - ns TINSU Transmit data setup time with respect to TXLSCKIN 1.0 - - ns TINH Transmit data hold time with respect to TXLSCKIN 1.0 - - ns TPROP Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN -- 3.5 ns Parameter Description Min Typ Max Units TCLKIN Transmit data input byte clock period - 51.44 - ns TINSU Transmit data setup time with respect to TXLSCKIN 1.0 - - ns TINH Transmit data hold time with respect to TXLSCKIN 1.0 - - ns TPROP Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN -- 30 ns Parameter Description Min Typ Max Units TRXCLKIN Receive clock period - 1.608 - ns TRXLSCK Receive data output byte clock period - 12.86 - ns TRXVALID Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT 4.0 - - ns TPW Pulse width of frame detection pulse FP - 12.86 - ns A1 A2 A2 A2 A2 TRXLSCK TRXCLKIN RXOUT [7:0] RXLSCKOUT RXCLKIN+ RXCLKIN- |
Similar Part No. - VSC8113QB2 |
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