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VSC7127T Datasheet(PDF) 6 Page - Vitesse Semiconductor Corporation |
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VSC7127T Datasheet(HTML) 6 Page - Vitesse Semiconductor Corporation |
6 / 12 page Data Sheet VSC7127/VSC7129 Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel VITESSE SEMICONDUCTOR CORPORATION Page 6 G52298-0, Rev 4.3 05/01/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Figure 4: REFCLK Timing Waveforms * Table 2: Reference Clock Requirements DC Characteristics (Over recommended operating conditions) NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements. Parameters Description Min Typ Max Units Conditions FR Frequency Range 105 107 MHz FO Frequency Offset -200 200 ppm Maximum frequency offset between transmit and receive reference clocks on one link DC Duty Cycle 35 65 % Measured at 1.5V TR, TF Rise and Fall Time 2.0 ns Between VIL(MAX) and VIH(MIN) Parameters Description Min Typ Max Units Conditions VOH Output HIGH voltage (TTL) 2.4 V IOH = -1.0mA VOL Output LOW voltage (TTL) 0.5 V IOL = +1.0mA VIH Input HIGH voltage (TTL) 2.0 5.5 V VIL Input LOW voltage (TTL) 0 0.8 V IIH Input HIGH current (TTL) 50 500 µA VIN =2.4V IIL Input LOW current (TTL) -500 µA VIN =0.5V ∆V OUT75 (1) TX output differential peak-to- peak voltage swing 1200 2200 mVp-p 75 Ω to V DD – 2.0 V ∆V OUT50 (1) TX output differential peak-to- peak voltage swing 1000 2200 mVp-p 50 Ω to V DD – 2.0 V ∆V IN (1) Receiver differential peak-to-peak input Sensitivity RX 400 2600 mVp-p Internally biased to VDD/2 VDD Supply voltage 3.14 3.47 V 3.3V±5% PD Power dissipation 707 902 mW Outputs open, VDD = VDD max. ±2% IDD Current (all supplies) 215 260 mA Outputs open, VDD = VDD max IDDA Current (VDDA)50 70 mA VDDA = VDD max REFCLK VIL(MAX) VIH(MIN) NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state. |
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