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SLG46534 Datasheet(PDF) 42 Page - Dialog Semiconductor |
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SLG46534 Datasheet(HTML) 42 Page - Dialog Semiconductor |
42 / 172 page SLG46534_DS_107 Page 41 of 171 SLG46534 reg <559:552> Matrix OUT: IN1 of LUT3_0 or Data Input of DFF3 69 reg <567:560> Matrix OUT: IN2 of LUT3_0 or RSTB (SETB) of DFF3 70 reg <575:568> Matrix OUT: IN0 of LUT3_1 or Clock Input of DFF4 71 reg <583:576> Matrix OUT: IN1 of LUT3_1 or Data Input of DFF4 72 reg <591:584> Matrix OUT: IN2 of LUT3_1 or RSTB (SETB) of DFF4 73 reg <599:592> Matrix OUT: IN0 of LUT3_2 or Clock Input of DFF5 74 reg <607:600> Matrix OUT: IN1 of LUT3_2 or Data Input of DFF5 75 reg <615:608> Matrix OUT: IN2 of LUT3_2 or RSTB (SETB) of DFF5 76 reg <623:616> Matrix OUT: IN0 of LUT3_3 or Clock Input of DFF6 77 reg <631:624> Matrix OUT: IN1 of LUT3_3 or Data Input of DFF6 78 reg <639:632> Matrix OUT: IN2 of LUT3_3 or RSTB (SETB) of DFF6 79 reg <647:640> Matrix OUT: IN0 of LUT3_4 or Clock Input of DFF7 80 reg <655:648> Matrix OUT: IN1 of LUT3_4 or Data Input of DFF7 81 reg <663:656> Matrix OUT: IN2 of LUT3_4 or RSTB (SETB) of DFF7 82 reg <671:664> Matrix OUT: IN0 of LUT3_5 or Delay2 Input (or Counter2 RST Input) 83 reg <679:672> Matrix OUT: IN1 of LUT3_5 or External Clock Input of Delay2 (or Counter2) 84 reg <687:680> Matrix OUT: IN2 of LUT3_5 85 reg <695:688> Matrix OUT: IN0 of LUT3_6 or Delay3 Input (or Counter3 RST Input) 86 reg <703:696> Matrix OUT: IN1 of LUT3_6 or External Clock Input of Delay3 (or Counter3) 87 reg <711:704> Matrix OUT: IN2 of LUT3_6 88 reg <719:712> Matrix OUT: IN0 of LUT3_7 or Delay4 Input (or Counter4 RST Input) 89 reg <727:720> Matrix OUT: IN1 of LUT3_7 or External Clock Input of Delay4 (or Counter4) 90 reg <735:728> Matrix OUT: IN2 of LUT3_7 91 reg <743:736> Matrix OUT: IN0 of LUT3_8 or Delay5 Input (or Counter5 RST Input) 92 reg <751:744> Matrix OUT: IN1 of LUT3_8 or External Clock Input of Delay5 (or Counter5) 93 reg <759:752> Matrix OUT: IN2 of LUT3_8 94 reg <767:760> Matrix OUT: IN0 of LUT3_9 or Delay6 Input (or Counter6 RST Input) 95 reg <775:768> Matrix OUT: IN1 of LUT3_9 or External Clock Input of Delay6 (or Counter6) 96 reg <783:776> Matrix OUT: IN2 of LUT3_9 97 reg <791:784> Matrix OUT: IN0 of LUT3_10 or Input of Pipe Delay 98 reg <799:792> Matrix OUT: IN1 of LUT3_10 or RSTB of Pipe Delay 99 reg <807:800> Matrix OUT: IN2 of LUT3_10 or Clock of Pipe Delay 100 reg <815:808> Matrix OUT: IN0 of LUT4_0 or Delay0 Input (or Counter0 RST/SET Input) 101 reg <823:816> Matrix OUT: IN1 of LUT4_0 or External Clock Input of Delay0 (or Counter0) 102 reg <831:824> Matrix OUT: IN2 of LUT4_0 or UP Input of FSM0 103 reg <839:832> Matrix OUT: IN3 of LUT4_0 or KEEP Input of FSM0 104 reg <847:840> Matrix OUT: IN0 of LUT4_1 or Delay1 Input (or Counter1 RST/SET Input) 105 reg <855:848> Matrix OUT: IN1 of LUT4_1 or External Clock Input of Delay1 (or Counter1) 106 reg <863:856> Matrix OUT: IN2 of LUT4_1 or UP Input of FSM1 107 Table 28. Matrix Output Table Register Bit Address Matrix Output Signal Function Note: For each Address, the two most significant bits are unused) Matrix Output Number |
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