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SLG46533 Datasheet(PDF) 87 Page - Dialog Semiconductor |
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SLG46533 Datasheet(HTML) 87 Page - Dialog Semiconductor |
87 / 185 page SLG46533_DS_114 Page 86 of 184 SLG46533 9.7 CNT/DLY/FSM Timing Diagrams 9.7.1 Delay mode (edge select: both, counter data: 3) CNT/DLY2...CNT/DLY6 9.7.2 Count mode (count data: 3), Counter reset (rising edge detect) CNT/DLY2...CNT/DLY6 Figure 36. Delay Mode Timing Diagram Figure 37. Counter Mode Timing Diagram Delay In RC osc: force power on (always running) Delay Output Asynchronous delay variable Asynchronous delay variable delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period Delay In RC osc: auto power on (powers up from delay in) Delay Output offset offset delay = offset + period x (counter data + 1) See offset in table 3 delay = offset + period x (counter data + 1) See offset in table 3 RESET_IN CLK Counter OUT Count start in 0 clk after reset 4 clk period pulse |
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