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SLG46200 Datasheet(PDF) 27 Page - Dialog Semiconductor |
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SLG46200 Datasheet(HTML) 27 Page - Dialog Semiconductor |
27 / 69 page 000-0046200-124 Page 22 of 64 SLG46200 11.0 Analog to Digital Converter (ADC) The Analog to Digital Converter in the SLG46200 is an 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC) which operates at a maximum sampling speed of 7.5kHz. User controlled inputs and outputs of the ADC are listed below: Inputs: • CH SELECTOR: Single-Ended Mode ADC Selection and Analog Input Mux Control Signal • IN+: Single-Ended Mode Input and Differential Mode Positive Input • IN-: Differential Mode Negative Input • EXT. VREF: ADC External Voltage Reference Input • EXT. CLK: ADC External Clock Input • PWR DOWN: ADC Power Down Signal Outputs: • PGA: Output of the PGA to ACMP0 • SER DATA: ADC serial output to PIN 3 • PAR DATA: ADC parallel data to either the PWM or DCMP0. • OUT CLK: ADC Clock Output to PIN 4 11.1 ADC Functional Diagram Figure 9. ADC Functional Diagram PGA ADC Power Down PGA (To ACMP0) SER DATA PAR DATA 1 0 EXT. CLK (PIN 4) CLK4ADC/64 reg <340> Bandgap (1.796V) EXT. VREF (PIN 8) Power divider (VDD * 0.547) 10 00 01 PWR DOWN ADC Programmable Gain Amplifier reg <342:341> 1 0 PIN 6 PIN 7 reg <350> ADC_sel ADC_gndoff_en reg <371> reg <353:351> reg <339> CH SELECTOR (PIN 2) Logic “1” VREF CLK IN- IN+ From Connection Matrix output <3> 0 1 0 1 reg <372> reg <373> From Connection Matrix output <12> S2P SPI output PIN 3 CH SELECTOR (PIN 2) |
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