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SLG46108 Datasheet(PDF) 27 Page - Dialog Semiconductor |
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SLG46108 Datasheet(HTML) 27 Page - Dialog Semiconductor |
27 / 70 page 000-0046108-108 Page 26 of 69 SLG46108 8.2 Matrix Output Table Table 18. Matrix Output Table Register Bit Address Matrix Output Signal Function Matrix Output Number reg <4:0> Pin 3 digital out source 0 reg <9:5> Pin 4 digital out source 1 reg <14:10> Pin 4 output enable 2 reg <19:15> in0 of LUT2_0 (Clock Input of DFF0) 3 reg <24:20> in1 of LUT2_0 (Data Input of DFF0) 4 reg <29:25> in0 of LUT2_1 (Clock Input of DFF1) 5 reg <34:30> in1 of LUT2_1 (Data Input of DFF1) 6 reg <39:35> in0 of LUT2_2 7 reg <44:40> in1 of LUT2_2 8 reg <49:45> in0 of LUT2_3 9 reg <54:50> in1 of LUT2_3 10 reg <59:55> in0 of LUT3_0 (Clock Input of DFF2 with nReset/nSet) 11 reg <64:60> in1 of LUT3_0 (Data input of DFF2 with nReset/nSet) 12 reg <69:65> in2 of LUT3_0 (nRST or nSET of DFF2 with nReset/nSet)13 reg <74:70> in0 of LUT3_1 (Clock Input of DFF3 with nReset/nSet) 14 reg <79:75> in1 of LUT3_1 (Data input of DFF3 with nReset/nSet) 15 reg <84:80> in2 of LUT3_1 (nRST or nSET of DFF3 with nReset/nSet)16 reg <89:85> in0 of LUT3_2 17 reg <94:90> in1 of LUT3_2 18 reg <99:95> in2 of LUT3_2 19 reg <104:100> in0 of LUT3_3 20 reg <109:105> in1 of LUT3_3 21 reg <114:110> in2 of LUT3_3 22 reg <119:115> in0 of LUT3_4 (Input of pipe delay) 23 reg <124:120> in1 of LUT3_4 (nRST of pipe delay) 24 reg <129:125> in2 of LUT3_4 (Clock of pipe delay) 25 reg <134:130> in0 of LUT4_0 (Input for Delay2 ext. clock or Counter2 external Clock) 26 reg <139:135> in1 of LUT4_0 (Input for Delay2 or counter2 reset input) 27 reg <144:140> in2 of LUT4_0 (Input for Counter2 FSM keep signal) 28 reg <149:145> in3 of LUT4_0 (Input for Counter2 FSM up signal) 29 reg <154:150> Input for Delay0 or Counter0 reset input 30 reg <159:155> Input for Delay1 or Counter1 reset input 31 reg <164:160> Input for Delay 0/1(Counter 0/1) external clock 32 reg <169:165> Input for Delay3 or Counter3 reset input 33 reg <174:170> Input for programmable delay (deglitch filter input) 34 reg <179:175> Power down for osc. (higher priority) (high = power down). 35 reg <184:180> Pin 6 digital out source 36 reg <189:185> Pin 7 digital out source 37 |
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