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TPS65917-Q1 Datasheet(PDF) 67 Page - Texas Instruments |
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TPS65917-Q1 Datasheet(HTML) 67 Page - Texas Instruments |
67 / 89 page PD PD 1.8 V I R disch arg e PD O t (ms) R (k ) C ( F) 3 : P u 67 TPS65917-Q1 www.ti.com SLVSCO4C – JULY 2015 – REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links: TPS65917-Q1 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated The value of the pulldown resistor should be chosen based on the desired discharge time and acceptable current draw in the OFF state, but no greater than 0.5 mA. Use Equation 6 to calculate the pulldown resistor based on the desired discharge time. where • tdischarge = discharge time of the VRTC output • RPD = pulldown resistance from the VRTC output to GND • CO = output capacitance on the VRTC line (typically 2.2 µF) (6) Because LDOVRTC is always on when VCC is supplied, additional current is drawn through the pulldown resistor. The output current of LDOVRTC while the PMIC is in OFF state should not exceed 0.5 mA. Use Equation 7 to calculate the pulldown current. where • IPD = current through the pulldown resistor • RPD = pulldown resistance from the VRTC regulator (7) To use comparators in the system: • The VSYS_HI and VSYS_LO thresholds are defined in the OTP. Software cannot change these levels. • After startup, the VSYS_MON comparator is automatically disabled. Software can select new threshold levels using the VSYS_MON register and then enable the comparators. • To have the same coding for rising and falling edge, the VSYS_MON comparator does not include hysteresis and thus can generate multiple interrupts when the voltage level is at threshold level. New interrupt generation has a 125-µs debounce time. This time lets software mask the interrupt and update the threshold level or disable the comparator before receiving a new interrupt. Figure 5-27 shows more details on VSYS_MON comparator. When the VSYS_MON comparator is enabled, and the internal buffer is bypassed, the input impedance at VCC_SENSE pin is 500 kΩ (typical). When the comparator is disabled, the VCC_SENSE pin is in the high-impedance state. If GPADC is enabled to measure channel 2 or channel 3, 40 kΩ is added in parallel to the corresponding comparator. See Table 5-9 for GPADC input range. To enable system voltage sensing above 5.25 V, an external resistive divider can be used. Internal buffers can be enabled by setting the OTP bit HIGH_VCC_SENSE to 1 to provide high impedance for the external resistive dividers. The maximum input level for the internal buffer is VCCA – 1 V. |
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