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TPS65917-Q1 Datasheet(PDF) 59 Page - Texas Instruments |
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TPS65917-Q1 Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 89 page  59 TPS65917-Q1 www.ti.com SLVSCO4C – JULY 2015 – REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links: TPS65917-Q1 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated 5.12 Control Interfaces The TPS65917-Q1 device has two, exclusive selectable (from factory settings) interfaces; 2 high-speed I2C interfaces (I2C1_SCL_SCK or I2C1_SDA_SDI and I2C2_SCL_SCE or I2C2_SDA_SDO) or 1 SPI (I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SDA_SDO, or I2C2_SCL_SCE). Both are used to fully control and configure the device and have access to all the registers. When the I2C configuration is selected (either I2C1_SCL_SCK or I2C1_SDA_SDI) a general purpose control (GPC) interface is dedicated to configure the device and the I2C2_SCL_SCE or I2C2_SDA_SDO interface, dynamic voltage scaling (DVS) is dedicated to dynamically change the output voltage of the SMPS converters. The DVS I2C interface has access only to the voltage scaling registers of the SMPS converters (R/W mode). 5.12.1 I 2C Interfaces The GPC I2C interface (I2C1_SCL_SCK and I2C1_SDA_SDI) is dedicated to access the configuration registers of all the resources of the system. The DVS I2C interface (I2C2_SCL_SCE and I2C_SDA_SDO) is dedicated to access the DVS registers independently from the GPC I2C. The control interfaces comply with the HS-I2C specification and support the following features: • Mode: Slave only (receiver and transmitter) • Speed: – Standard mode (100 kbps) – Fast mode (400 kbps) – High-speed mode (3.4 Mbps) • Addressing: 7-bit mode addressing device The following features are not supported: • 10-bit addressing • General call • Master mode (bus arbitration and clock generation) I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus Specification and user manual, Rev 03, June 2007). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, the SDA and SCL lines are pulled high. All the I2C- compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the start and stop of data transfers. A slave device receives data, transmits data, or both on the bus under control of the master device. The data transfer protocol for standard and fast modes is exactly the same. In this data sheet, these modes are referred to as F/S mode. The protocol for high-speed (HS) mode is different from F/S mode. 5.12.1.1 I2C Implementation The TPS65917-Q1 standard I2C 7-bit slave device address is set to 010010xx (binary) where the two least-significant bits are used for page selection. The device is organized in five internal pages of 256 bytes (registers) as follows: • Slave device address 0x48: Power registers • Slave device address 0x49: Interfaces and auxiliaries • Slave device address 0x4A: Trimming and test • Slave device address 0x4B: OTP • Slave device address 0x12: DVS The device address for the DVS I2C interface is set to 0x12. |
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