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TPS65916 Datasheet(PDF) 37 Page - Texas Instruments |
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TPS65916 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 89 page  Switch-on event RESET_OUT Power-up sequence POWERHOLD Device maintained ACTIVE for 8 seconds Device switch off starts with no delay VCC_SENSE VRTC VIO RC 32kHz RESET_OUT t2 t1 37 TPS65916 www.ti.com SLVSD09B – MARCH 2016 – REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links: TPS65916 Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated 5.3.4 Device Power Up Timing Figure 5-4 shows the timing diagram of the TPS65916 after the first supply detection. Figure 5-4. TPS65916 Power-Up Sequence After FSD The time t1 is the delay from VCC crossing the POR threshold to VIO rising up. The time t1 must be at least 6 ms. If the time from VCC to VIO is less than 6 ms, the VIO buffers will be supplied while the OTP is still being initialized, which could cause glitches on any VIO output buffer. Supplying VIO at least 6 ms after supplying VCC ensures that the OTP is initialized and output buffers are held low when VIO is supplied. The time t2 is the delay between the start of the power-up sequence and the RESET_OUT release. The RESET_OUT resource is released when the power-up sequence is complete. The duration of the power- up sequence depends on OTP programming. 5.3.5 Power-On Acknowledge The PMIC is designed to support the following power-on acknowledge modes: POWERHOLD mode and AUTODEVON mode. 5.3.5.1 POWERHOLD Mode In POWERHOLD mode, the power-on acknowledge is received through a dedicated pin, POWERHOLD. When an ON request is received, the device initiates the power-up sequence and asserts the RESET_OUT pin high while the device is in the ACTIVE state (reset released). The device remains in ACTIVE state for a fixed delay of 8 seconds and then automatically shuts down. During this timeframe, to keep the device active, the host processor must assert and keep the POWERHOLD pin high. The device interprets a the high to low transition of the POWERHOLD pin as an OFF request. Figure 5-5 shows the POWERHOLD mode timing diagram. Figure 5-5. POWERHOLD Mode Timing Diagram |
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