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IDT72V36104L15PF Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72V36104L15PF Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 36 page COMMERCIALTEMPERATURERANGE IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2 9 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF IDT72V3684L10 IDT72V3684L15 IDT72V3694L10 IDT72V3694L15 IDT72V36104L10 IDT72V36104L15 Symbol Parameter Min. Max. Min. Max. Unit tA Access Time, CLKA ↑ toA0-A35andCLKB↑toB0-B35 2 6.5 2 10 ns tWFF Propagation Delay Time, CLKA ↑ to FFA/IRA and CLKB↑ 2 6.5 2 8 ns to FFB/IRB tREF Propagation Delay Time, CLKA ↑ to EFA/ORAandCLKB↑ 1 6.5 1 8 ns to EFB/ORB tPAE Propagation Delay Time, CLKA ↑ to AEA and CLKB↑ to 1 6.5 1 8 ns AEB tPAF Propagation Delay Time, CLKA ↑ to AFAand CLKB↑ to 1 6.5 1 8 ns AFB tPMF Propagation Delay Time, CLKA ↑ to MBF1 LOW or MBF2 0 6.5 0 8 ns HIGH and CLKB ↑ to MBF2 LOW or MBF1 HIGH tPMR Propagation Delay Time, CLKA ↑ to B0-B35(1)and CLKB↑ 38 2 10 ns to A0-A35(2) tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to 3 6.5 2 10 ns B0-B35 valid tRSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB 110 1 15 ns LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH tEN Enable Time, CSA or W/RA LOW to A0-A35 Active and 2 6 2 10 ns CSB LOW and W/RB HIGH to B0-B35 Active tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high- 1 6 1 8 ns impedance and CSB HIGH or W/RB LOW to B0-B35 at high-impedance NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. (Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant) |
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