COMMERCIALTEMPERATURERANGE

BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2

11

Once the Master Reset (

MRS1, MRS2) input is HIGH, a LOW on the BE/

FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and

CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready

function (ORA, ORB) to indicate whether or not there is valid data at the data

outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)

to indicate whether or not the FIFO memory has any free space for writing.

In the FWFT mode, the first word written to an empty FIFO goes directly to data

outputs, no read request necessary. Subsequent words must be accessed

by performing a formal read operation.

Following Master Reset, the level applied to the BE/

FWFTinputtochoose

the desired timing mode must remain static throughoutFIFOoperation.Refer

to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

Four registers in the IDT72V3684/72V3694/72V36104 are used to hold the

offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-

Emptyflag(

AEB)OffsetregisterislabeledX1andthePortAAlmost-Emptyflag

(

AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset

register is labeled Y1 and the Port B Almost-Full flag (

AFB) Offset register is

labeled Y2. The index of each register name corresponds to its FIFO number.

TheoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofaFIFO,

programmed in parallel using the FIFO’s Port A data inputs, or programmed

in serial using the Serial Data (SD) input (see Table 1).

FS0/SD, FS1/

SEN and FS2 function the same way in both IDT Standard

and FWFT modes.

— PRESET VALUES

ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith

oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH

or LOW during a master reset. For example, to load the preset value of 64 into

X1andY1,FS0,FS1andFS2mustbeHIGHwhenFlFO1reset(

MRS1)returns

HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the

preset values in the same way with FIFO2 Master Reset (

MRS2), toggled

simultaneously with FIFO1 Master Reset (

MRS1). For relevant preset value

loading timing diagram, see Figure 3.

— PARALLEL LOAD FROM PORT A

To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master

Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1

LOWduringtheLOW-to-HIGHtransitionofMRS1andMRS2.ThestateofFS2

at this point of reset will determine whether the parallel programming method

has Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag

Programming Flag Offset setup . It is important to note that once parallel

programming has been selected during a Master Reset by holding both FS0

& FS1 LOW, these inputs must remain LOW during all subsequent FIFO

operation. They can only be toggled HIGH when future Master Resets are

performed and other programming methods are desired.

After this reset is complete, the first four writes to FIFO1 do not store data in

RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-

InterspersedParitymodethePortAdatainputsusedbytheOffsetregistersare

(A13-A0), (A14-A0), or (A15-A0) for the IDT72V3684, IDT72V3694, or

IDT72V36104, respectively. For Interspersed Parity mode the Port A data

inputs used by the Offset registers are (A14-A9, A7-A0), (A15-A9, A7-A0), or

(A16-A9, A7-A0) for the IDT72V3684, IDT72V3694, or IDT72V36104,

respectively. The highest numbered input is used as the most significant bit of

the binary number in each case. Valid programming values for the registers

range from 1 to 16,380 for the IDT72V3684; 1 to 32,764 for the IDT72V3694;

and 1 to 65,532 for the IDT72V36104. After all the offset registers are

NOTES:

1. X1 register holds the offset for

AEB; Y1 register holds the offset for AFA.

2. X2 register holds the offset for

AEA; Y2 register holds the offset for AFB.

3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.

4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.

5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.

FS2

FS1/

SEN

FS0/SD

MRS1

MRS2

HH

H

↑

X64

X

HH

H

X

↑

X64

HH

L

↑

X16

X

HH

L

X

↑

X16

HL

H

↑

X8

X

HL

H

X

↑

X8

LH

H

↑

X

256

X

LH

H

X

↑

X

256

LL

H

↑

X

1,024

X

LL

H

X

↑

X

1,024

LH

L

↑↑

Serial programming via SD

Serial programming via SD

HL

L

↑↑

LL

L

↑↑

TABLE 1 — FLAG PROGRAMMING