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M470L3223DT0-CA2 Datasheet(PDF) 7 Page - Samsung semiconductor |
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M470L3223DT0-CA2 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 16 page M470L3223DT0 Rev. 0.0 Dec. 2001 DDR SDRAM IDD spec table * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) Unit Notes IDD0 720 640 600 mA IDD1 960 880 800 mA IDD2P 24 24 24 mA IDD2F 200 160 144 mA IDD2Q 160 144 128 mA IDD3P 280 240 200 mA IDD3N 440 360 320 mA IDD4R 1360 1120 960 mA IDD4W 1360 1120 920 mA IDD5 1440 1320 1200 mA IDD6 Normal 24 24 24 mA Low power 12 12 12 mA Optional IDD7A 2600 2240 1880 mA < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 2. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP |
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